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73K222AU Single-Chip Modem Modem with UART
April 2000
DESCRIPTION
The 73K222AU is a compact, high-performance modem which includes a 8250A/16C450 compatible UART with the 1200 bit/s modem function on a single chip. Based on the 73K222L 5V low power CMOS modem IC, the 73K222AU is the perfect modem/UART component for integral modem applications. It is ideal for applications such as portable terminals and laptop computers. The 73K222AU is the first fully featured modem IC which can function as an intelligent modem in integral applications without requiring a separate dedicated microcontroller. It provides for data communication at 1200, 600, and 300 bit/s in a multi-mode manner that allows operation compatible with both Bell 212A/103 and CCITT V.22/V.21 standards. The digital interface section contains a high speed version of the industry standard 8250A/16C450 UART, commonly used in personal computer products. A unique feature of the 73K222AU is that the UART section can be used without the modem function, providing an additional asynchronous port at no added cost. The 73K222AU is designed in CMOS technology and operates from a single +5V supply. Available packaging includes 40-pin DIP or 44-pin PLCC for surface mount applications.
FEATURES
* Modem/UART combination optimized for integral bus applications * Includes features of 73K222L single-chip modem * Fully compatible 16C450/8250 UART with 8250B or 8250A selectable interrupt emulation * High speed UART will interface directly with high clock rate bus with no wait states * Single-port mode allows full modem and UART control from CPU bus, with no dedicated microprocessor required * Dual-port mode suits conventional designs using local microprocessor for transparent modem operation * Complete modem functions for 1200 bit/s (Bell 212A, V.22) and 0-300 bit/s (Bell 103, V.21) * Includes DTMF generator, carrier, callprogress and precise answer-tone detectors for intelligent dialing capability * On chip 2-wire/4-wire hybrid driver and offhook relay buffer * Speaker output with four-level software driven volume control * Low power CMOS (40 mW) with power down mode (15 mW) * Operates from single +5V supply
BLOCK DIAGRAM
TXD XTL1 XTL2 CLK
UD0 UD1 1.8432 MHz UD2 UD3 UD4 UD5 UD6 UD7 UA0 UA1 UA2 8250A / 16C450 UART INTERNAL DATA 73K222AL 2 2W/4W HYBRID
TXA1 TXA2 RXA SPKR ( ( ) / MA0 ) / MA1
(UA3) / MA2 DATA / ( /( ) )
/ (N/C) ( ( RXD-INPUT INT OUT1 OH RELAY DRIVER ) / DCLK )/
INTRPT
(
) PRST
RESET
RXD
VDD VREF GND ISET STNDLN
73K222AU Single-Chip Modem with UART
FUNCTIONAL DESCRIPTION
The 73K222AU integrates an industry standard 8250/16C450 UART function with the modem capability provided by the 73K222L single chip modem IC. The 73K222AU is designed specifically for integral microprocessor bus intelligent modem products. These designs typically require the standard 8250 or higher speed 16450 UART to perform parallel-to-serial and serial-to-parallel conversion process necessary to interface a parallel bus with the inherently serial modem function. The 73K222AU provides a highly integrated design which can eliminate multiple components in any integral bus modem application, and is ideal for internal PC modem applications. The 73K222AU includes two possible operating modes. In the dual-port mode, the device is suitable for conventional plug-in modem card designs which use a separate local microprocessor for command interpretation and control of the modem function. In this mode, a dedicated microcontroller communicates with the 73K222AU using a separate serial command port. In the single-port mode the main CPU can control both the UART and modem function using the parallel data bus. This allows very efficient modem design with no local microprocessor required for dedicated applications such as laptop PC's or specialized terminals. To make designs more space efficient, the 73K222AU includes the 2-wire to 4-wire hybrid drivers, off-hook relay driver, and an audio monitor output with software volume control for audible call progress monitoring. As an added feature the UART function can be used independent of the modem function, providing an added asynchronous port in a typical PC application with no additional circuitry required. UART FUNCTION (16C450) The UART section of the 73K222AU is completely compatible with the industry standard 16C450 and the 8250 UART devices. The bus interface is identical to the 16450, except that only a single polarity for the control signals is supported. The register contents and addresses are also the same as the 16C450. To insure compatibility with all existing releases of the 8250 UART design, external circuitry normally used in PC applications to emulate 8250B or 8250A interrupt operation has been included on the 73K222AU. A select line is then provided to enable the desired interrupt operation. 2 The UART used in the 73K222AU can be used with faster bus read and write cycles than a conventional 16C450 UART. This allows it to interface directly with higher clock rate microprocessors with no need for external circuitry to generate wait states. The primary function of the UART is to perform parallel-to-serial conversion on data received from the CPU and serial-to-parallel conversion on data received from the internal modem or an external device. The UART can program the number of bits per character, parity bit generation and checking, and the number of stop bits. The UART also provides break generation and detection, detection of error conditions, and reporting of status at any time. A prioritized maskable interrupt is also provided. The UART block has a programmable baud rate generator which divides an internal 1.8432 MHz clock to generate a clock at 16 x the data rate. The data rate for the transmit and receive sections must be the same. For DPSK modulation, the data rate must be 1200 Hz or 600 Hz. For FSK modulation, the data rate must be 300 Hz or less. The baud generator can create a clock that supports digital transfer at up to 115.2 kHz. The output of the baud generator can be made available at the CLK pin under program control. MODEM FUNCTION (73K222AL) The modem section of the 73K222AU provides all necessary analog functions required to create a single chip Bell 212A/103 and CCITT V.22/V.21 modem, controlled by the system CPU or a local dedicated microprocessor. Asynchronous 1200 bit/s DPSK (Bell 212A and V.22) and 300 baud FSK (Bell 103 and V.21) modes are supported. The modem portion acts as a peripheral to the microprocessor. In both modes of operation, control information is stored in register memory at specific address locations. In the single-port mode, the modem section can be controlled through the 16C450 interface, with no external microcontroller required. The primary analog blocks are the DPSK modulator/demodulator, the FSK modulator/ demodulator, the high and low band filters, the AGC, the special detect circuitry, and the DTMF tone generator. The analog functions are performed with switched capacitor technology.
73K222AU Single-Chip Modem with UART
PSK MODULATOR / DEMODULATOR The 73K222AU modulates a serial bit stream into dibit pairs that are represented by four possible phase shifts as prescribed by the Bell 212A or V.22 standard. The baseband signal is then filtered to reduce intersymbol interference on the band limited 2-wire PSTN line. Transmission occurs using either a 1200 Hz (originate mode) or 2400 Hz carrier (answer mode). Demodulation is the reverse of the modulation process, with the incoming analog signal eventually decoded into dibits and converted back to a serial bit stream. The demodulator also recovers the clock which was encoded into the analog signal during modulation. The demodulator decodes either a 1200 Hz carrier (originate carrier) or a 2400 Hz carrier (answer carrier). The 73K222AU uses a phase-locked-loop coherent demodulation technique that offers inherently better performance than typical DPSK demodulators used by other manufacturers. FSK MODULATOR/DEMODULATOR The FSK modulator frequency modulates the analog output signal using two discrete frequencies to represent the binary data. In Bell 103, the standard frequencies of 1270 Hz and 1070 Hz (originate mark and space) and 2225Hz and 2025 Hz (answer mark and space) are used. V.21 mode uses 980 Hz and 1180 Hz (originate, mark and space) or 1650 Hz and 1850 Hz (answer, mark and space). Demodulation involves detecting the received frequencies and decoding them into the appropriate binary value. PASSBAND FILTERS AND EQUALIZERS A high and low band filter is included to shape the amplitude and phase response of the transmit signal and provide compromise delay equalization and rejection of out-of-band signals in the receive channel. Amplitude and phase equalization is necessary to compensate for distortion of the transmission line and to reduce intersymbol interference in the band limited receive signal. The transmit signal filtering approximates a 75% square root of raised Cosine frequency response characteristic. AGC The automatic gain control maintains a signal level at the input to the demodulators which is constant to within 1 dB. It corrects quickly for increases in signal which would cause clipping, and provides a total dynamic range of >45 dB. SPECIAL DETECT CIRCUITRY The special detect circuitry monitors the received analog signal to determine status or presence of carrier, call-progress tones, answer tone, and weak received signal (long loop condition). An unscrambled mark signal is also detected when the received data out of the DPSK demodulator before the descrambler has been high for 165.5 mS 13.5 mS. The appropriate status bit is set when one of these conditions changes and an interrupt is generated for all monitored conditions except long loop. The interrupts are disabled (masked) when the enable interrupt bit is set to a 0. DTMF GENERATOR The DTMF generator will output one of 16 standard dual-tones determined by a 4-bit binary value and TX DTMF mode bit previously loaded into the tone register. Tone generation is initiated when the DTMF mode is selected and the transmit enable (CR0 bit D1) is changed from a 0 to a 1. TEST FEATURES Test features such as analog loopback (ALB), remote digital loopback, local digital loopback, and internal pattern generators are also included. LINE INTERFACE The line interface of the 73K222AU consists of a two-to-four wire hybrid, and an off-hook relay driver. The two-to-four wire converter has a differential transmit output and requires only a line transformer and an external impedance matching resistor. Fourwire operation is also available by simply using either of the transmit output signals. The relay driver output of the 73K222AU is an open drain signal capable of sinking 20 mA, which can control a line closure relay used to take the line off hook and to perform pulse dialing. AUDIO MONITOR An audio monitor output is provided which has a software programmable volume control. Its output is the received signal. The audio monitor output can directly drive a high impedance load, but an external power amplifier is necessary to drive a low-impedance speaker.
3
73K222AU Single-Chip Modem with UART
PIN DESCRIPTION
GENERAL NAME VDD GND VREF DIP 40 20 19 PLCC 44 22 21 TYPE I I O DESCRIPTION +5V Supply 10%, bypass with a 0.1 and a 22 F capacitor to GND System Ground VREF is an internally generated reference voltage which is externally bypassed by a 0.1 F capacitor to the system ground. The analog current is set by connecting this pin to VDD through a 2 M resistor. ISET should be bypassed to GND. Alternatively, an internal bias can be selected by connecting ISET to GND, which will result in a larger worst-case supply current due to the tolerance of on-chip resistors. Bypass with 0.1 F capacitor if resistor is used. These pins are connections for the internal crystal oscillator requiring an 11.0592 MHz crystal. XTL2 can also be TTL driven from an external clock. Connect a 10 M resistor from XTL1 to ground and a 1 M resistor from XTL1 to XTL2 Output Clock. This pin is selectable under processor control to be either the crystal frequency (which might be used as a processor clock) or the output of the baud generator. Reset. An active signal (high) on this pin will put the chip into an inactive state. The control register bits (except the Receiver Buffer, Transmitter Holding, and Divisor latches) will be reset. The output of the CLK pin will be set to the crystal frequency. An internal pull-down resistor permits power-on reset using a 0.1 F capacitor connected to the 5V supply. Single-port mode select (active high). In a single-port system there is no local microprocessor and all the modem control is done through the 16C450 parallel bus interface. The local microprocessor interface is replaced with UART control signals which allow the device to function as a digital UART as well as modem.
ISET
9
11
I
XTL1 XTL2
25 24
27 26
I I
CLK
21
23
O
RESET
10
12
I
STNDLN
15
17
I
4
73K222AU Single-Chip Modem with UART
UART INTERFACE NAME UA2-UA0 UA3 DIP 37-39 12 PLCC 41-43 14 TYPE I I DESCRIPTION UART Address. These pins determine which of the UART registers is being selected during a read or write on the UART data bus. The contents of the DLAB bit in the UART's Line Control Register also control which register is referenced. In single-port mode, UA0-UA3 are latched when ADS goes high. In dual-port, only UA0-UA2 are used. (3 state) UART Data. Data or control information to the UART registers is carried over these lines. Data Input Strobe. A low on this pin requests a read of the internal UART registers. Data is output on the D0-D7 lines if DISTR and CS@ are active. Data Output Strobe. A low on this pin requests a write of the internal UART registers. Data on the D0-D7 lines are latched on the rising edge of DOSTR. Data is only written if both DOSTR and CS@ are active. Chip Select. A low on this pin allows a read or write to the UART registers to occur. In single port mode, CS@ is latched on ADS. (3 state) UART Interrupt. This signal indicates that an interrupt condition on the UART side has occurred. If the Enable 8250A interrupt bit in the interrupt Enable Register is 0 the interrupt is gated by the DISTR signal to provide compatibility with the 8250B. The output can be put in a high impedance state with the OUT2 register bit in the Modem Control Register. In singleport mode, INTRPT also becomes valid when a modem interrupt signal is generated by the modem section's Detect Register. Function is determined by STNDLN pin and bit 7, Tone Control Register: STNDLN 0 1 X D7 0 0 1 RXD outputs data received by modem. RXD is electrically an input but signal is ignored. RXD is a serial input to UART.
UDO-UD7
DISTR
27-34 35
30-37 38
I/O I
DOSTR
36
39
I
CS@
1
2
I
INTRPT
5
7
O
RXD
6
8
I/O
5
73K222AU Single-Chip Modem with UART
UART INTERFACE (continued) NAME TXD DIP 7 PLCC 9 TYPE O DESCRIPTION Function is determined by STNDLN pin and bit 7, Tone Control Register: STNDLN 0 1 X ANALOG / LINE INTERFACE TXA1 TXA2 3 4 4 5 O O (differential) Transmitted Analog. These pins provide the analog output signals to be transmitted to the phone line. The drivers will differentially drive the impedance of the line transformer and the line matching resistor. An external hybrid can also be built using TXA1 as a single ended transmit signal. Received Analog. This pin inputs analog information that is being received by the two-to-four wire hybrid. This input can also be taken directly from an external hybrid. Speaker Output. This pin outputs the received signal through a programmable attenuator stage, which can be used for volume control and disabling the speaker. Off-hook relay driver. This signal is an open drain output capable of sinking 20 mA and is used for controlling a relay. The output is the complement of the OH register bit in CR3. D7 0 0 1 TXD is a serial output of UART. TXD is forced to a mark. TXD is a serial output of UART.
RXA
16
18
I
SPKR
17
19
O
OH
18
20
O
6
73K222AU Single-Chip Modem with UART
UART CONTROL INTERFACE (STNDLN = 1) (See Figure 1: Single-port mode) NAME
ADS
DIP 23
PLCC 25
TYPE I
DESCRIPTION Address Strobe. ADS is used to latch address and chip select to simplify interfacing to a multiplexed Address/Data Bus. UA0UA3 and CS@ are latched when the ADS signal goes high. UART Address Bit 3. UA3 is used in single-port mode to address the modem registers from the 16C450 interface. If UA3 is 0, the normal 16C450 registers are addressed by UA0-UA2 and if UA3 is 1, the modem registers are addressed. UA3 is latched when ADS goes high. Clear to Send. This pin is the complement of CTS bit in the Modem Status Register. The signal is used in modem handshake control to signify that communications have been established and that data can be transmitted. Data Set Ready. This pin is the complement of DSR bit in the Modem Status Register. The signal is used in modem handshake to signify that the modem is ready to establish communications. Data Carrier Detect. This pin is the complement of DCD bit in the Modem Status Register. The signal is used in modem control handshake to signify that the modem is receiving a carrier. Data Terminal Ready. The DTR output is programmed through a bit in the Modem Control Register. The signal is used in modem handshake to signify that the 16C450 is available to communicate. Request to Send. The RTS output is programmed through a bit in the Modem Control Register. The signal is used in modem handshake to signify that the 16C450 has data to transmit. Ring Indicator. This Indicates that a telephone ringing signal is being received. This pin is the complement of the RI bit in the Modem Status Register.
UA3
12
14
I
CTS
14
16
I
DSR
13
15
I
DCD
11
13
I
DTR
22
24
O
RTS
2
3
O
RI
8
10
I
7
73K222AU Single-Chip Modem with UART
PIN DESCRIPTION (continued)
MICROPROCESSOR INTERFACE (STNDLN = 0) (See Figure 2: Dual-port mode) NAME MA0-MA2 DIP 12-14 PLCC 14-16 TYPE I DESCRIPTION Modem Address Control. These lines carry register addresses for the modem registers and should be valid throughout any read or write operation. Serial Control Data. Serial control data to be read/written is clocked in/out on the falling edge of the DCLK pin. The direction of data transfer is controlled by the state of the RD pin. If the RD pin is active (low) the DATA line is an output. Conversely, if the RD pin is inactive (high) the DATA line is an input. Read. A low on this input informs the 73K222AU that control data or status information is being read by the processor from a modem register. Write. A low on this input informs the 73K222AU that control data or status information is available for writing into a modem register. The procedure for writing is to shift in data LSB first on the DATA pin for eight consecutive cycles of DCLK and then to pulse WR low. Data is written on the rising edge of WR. Data Clock. The falling edge of this clock is used to strobe control data for the modem registers in or out on the DATA pin. The normal procedure for a write is to shift in data LSB first on the DATA pin for eight consecutive cycles of DCLK and then to pulse WR low. Data is written on the rising edge of WR. The falling edge of the RD signal must continue for eight cycles of DCLK in order to read all eight bits of the reference register. Read data is provided LSB first. Data will not be output unless the RD signal is active. (with weak pull-up) Modem Interrupt. This output signal is used to inform the modem processor that a change in a modem detect flag has occurred. The processor must then read the Modem Detect Register to determine which detect triggered the interrupt. INT will stay active until the processor reads the Modem Detect Register or does a full reset. Microprocessor Reset. This output signal is used to provide a hardware reset to the microprocessor. This signal is high if the RESET pin is high or the MCR bit D3 (OUT1) bit is set.
DATA
22
24
I/O
RD
23
25
I
WR
26
28
I
DCLK
11
13
I
INT
2
3
O
MPRST*
8
10
O
* NOTE:
The PRST pin is an upgraded function which was not included in the initial definition of the 73K222AU.
8
STNDLN = 1 VDD VREF GND ISET XTAL1 XTAL2 CLK
N/C
RELAY DRIVER POWER CLOCK GENERATOR
BUS GATEWAY
MODEM CONTROL REGISTER (CONTROL REGISTER 0) (CONTROL REGISTER 1) (TONE REGISTER) 1.8432 MHz
TWO PORT SCRATCH REGISTER
MODEM INTERRUPT LOGIC (DETECT REGISTER)
SPEAKER GAIN CONTROL CALL PROGRESS DETECTOR ANTI-ALIS LPF
16C450 UART CONTROL REGISTERS (LINE CONTROL REGISTER) (LINE STATUS REGISTER) (MODERN CONTROL REGISTER) MODEM STATUS REGISTER) MODEM CONTROL BITS 1.8432 MHz BAUDOUT SCRAMBLER DPSK MODULATOR ADDITIONAL CONTROL REGISTERS (CONTROL REGISTER 2) (UART CONTROL REGISTER)
SPKR
UD0-UD7
RXA
UA0
UA1
BAUD GENERATOR (DIVISOR LATCH LS) (DIVISOR LATCH MS)
UA2 FSK MODULATOR DIGITAL LOOPBACK UNSCRAMBLED MARK (RDL) DETECTOR
UA3
UART (8250) SELECT LOGIC
TRANSMITTER (TRANSMIT HOLDING REGISTER)
HIGH BAND FILTER
LOW BAND FILTER
RST
DESCRAMBLER
DPSK MODULATOR
AGC TXA1 LONG LOOP DETECTOR ANALOG LOOPBACK DIFFERENTIAL HYBRID DRIVER TXA2
9
+V FSK MODULATOR TXD RXD
RECEIVER (RECEIVER BUFFER REGISTER)
INTERRUPT LOGIC (INTERRUPT ENABLE REGISTER) (INTERRUPT ID REGISTER)
CARRIER DETECTOR
DTMF GENERATOR ANSWER TONE DETECTOR
INTRPT
FIGURE 1: Single-Port Mode
73K222AU Single-Chip Modem with UART
In the single-port mode, the 73K222AU is designed to be accessed only by the main CPU using the same parallel bus utilized for data transfer. This mode is enabled when the STNDLN pin is at a logic "1". In the single port mode, internal registers are accessed by the main CPU to
configure both the UART section and the modem function, eliminating the need for a separate microcontroller. In this mode, multiplexed pins provide the CTS, DSR, DTR, DED and RI signals normally associated with the UART function. A separate pin, ADS, is used for bus control.
STNDLN = 1 MA1 VDD VREF GND ISET XTAL1 XTAL2 CLK
MA0
MA2
DATA
DCLK
MODEM SELECT LOGIC AND DATA SHIFT REGISTER POWER CLOCK GENERATOR
RELAY DRIVER
BUS GATEWAY 1.8432 MHz
MODEM CONTROL REGISTER (CONTROL REGISTER 0) (CONTROL REGISTER 1) (TONE REGISTER)
TWO PORT SCRATCH REGISTER
MODEM INTERRUPT LOGIC (DETECT REGISTER)
73K222AU Single-Chip Modem with UART
SPEAKER GAIN CONTROL CALL PROGRESS DETECTOR ANTI-ALIS LPF
SPKR
OUT1 MODEM CONTROL BITS 1.8432 MHz BAUDOUT SCRAMBLER DPSK MODULATOR
16C450 UART CONTROL REGISTERS (LINE CONTROL REGISTER) (LINE STATUS REGISTER) (MODERN CONTROL REGISTER) MODEM STATUS REGISTER) ADDITIONAL CONTROL REGISTERS (CONTROL REGISTER 2) (UART CONTROL REGISTER)
UD0-UD7
RXA
UA0
UA1
BAUD GENERATOR (DIVISOR LATCH LS) (DIVISOR LATCH MS)
UA2 FSK MODULATOR DIGITAL LOOPBACK UNSCRAMBLED MARK (RDL) DETECTOR
UA3
UART (8250) SELECT LOGIC
TRANSMITTER (TRANSMIT HOLDING REGISTER)
HIGH BAND FILTER
LOW BAND FILTER
RST
DESCRAMBLER
DPSK MODULATOR
AGC DIFFERENTIAL HYBRID DRIVER LONG LOOP DETECTOR ANALOG LOOPBACK TXA1 TXA2
10
FSK MODULATOR TXD RXD
RECEIVER (RECEIVER BUFFER REGISTER)
INTERRUPT LOGIC (INTERRUPT ENABLE REGISTER) (INTERRUPT ID REGISTER)
CARRIER DETECTOR
DTMF GENERATOR ANSWER TONE DETECTOR
PRST
FIGURE 2: Dual-Port Mode
The dual-port mode allows use of a dedicated microprocessor for control of the modem function, and is enabled when the STNDLN pin = "0". This mode is useful for conventional plug-in card modem designs where it is necessary to make the modem function transparent to the main CPU. In this mode, the 73K222AU's multiplexed pins from the serial command bus used to communicate with the external microprocessor. The RI, CTS, DSR, DTR, and DCD logic functions must then be implemented using ports
The serial control interface allows access to the control and status registers via a serial command port. In this mode the MA0, MA1, and MA2 lines provide register addresses for data passed through the DATA pin under control of the RD and WR lines. A read operation is initiated when the RD line is taken low. The next eight cycles of DCLK will then transfer out eight bits of the selected address location LSB first. A write takes place by shifting in eight bits of data LSB first for eight consecutive cycles of DCLK. WR is then pulsed low and data transfer into the selected register occurs on the rising edge of WR.
73K222AU Single-Chip Modem with UART
UART CONTROL REGISTER OVERVIEW
DATA BIT NUMBER UART ADDRESS UA3-UA0*
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
RECEIVER BUFFER REGISTER (READ ONLY) TRANSMIT HOLDING REGISTER (WRITE ONLY) INTERRUPT ENABLE REGISTER INTERRUPT ID REGISTER (READ ONLY) LINE CONTROL REGISTER MODEM CONTROL REGISTER LINE STATUS REGISTER MODEM STATUS REGISTER (READ ONLY) SCRATCH REGISTER
RBR
0000 DLAB = 0
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
THR
0000 DLAB = 0
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IER
0001 DLAB = 0
0
0
0
ENABLE 8250A/ 16C450 INTERRUPT
ENABLE MODEM STATUS INTERRUPT
ENABLE REC. LINE STATUS INTERRUPT INTERRUPT ID BIT 1 NUMBER OF STOP BITS (STB) PRST (OUT1 IN 16C450) PARITY ERROR (PE) TRAILING EDGE RING INDICATOR (TERI)
ENABLE THR EMPTY INTERRUPT INTERRUPT ID BIT 0 WORD LENGTH SELECT 1 (WLS1) REQUEST TO SEND (RTS) OVERRUN ERROR (OE) DELTA DATA SET READY (DDSR)
ENABLE REC. DATA AVAILABLE INTERRUPT "0" IF INTERRUPT PENDING WORD LENGTH SELECT 0 (WLS0) DATA TERMINAL READY (DTR) DATA READY (DR) DELTA CLEAR TO SEND (DCTS)
IIR
0010
0
0
0
0
0
LCR
0011
DIVISOR LATCH ACCESS (DLAB)
SET BREAK
STICK PARITY
EVEN PARITY SELECT (EPS)
PARITY ENABLE (PEN) ENABLE INTERRUPT (OUT2 IN 16C450) FRAMING ERROR (FE) DELTA DATA CARR. DETECT (DDCD)
MCR
0100
0
0
0
LOOP
LSR
0101
0
TRANSMIT SHIFT REG EMPTY (TSRE) RING INDICATOR (RI)
TRANSMIT HOLDING REGISTER EMPTY(THRE) DATA SET READY (DSR)
BREAK INTERRUPT (BI) CLEAR TO SEND (CTS)
MSR
0110
DATA CARRIER DETECT (DCD)
SCR
0111
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DIVISOR LATCH (LS) DIVISOR LATCH (MS)
DLL
0000 DLAB = 1
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DLM
0001 DLAB = 1
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
* In single-port mode (STNDLN pin = 1), all four address lines UA3-UA0 are used to address the UART Control Registers. * In dual-port mode (STNDLN pin = 0), only three address lines UA2-UA0 are used to address the UART Control Registers, the UA3 pin becomes the MA2 pin in this mode.
11
73K222AU Single-Chip Modem with UART
MODEM CONTROL REGISTER OVERVIEW
ADDRESS STNDLN 0 1 MA2UA3MA0 UA0 000 1000 DATA BIT NUMBER
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
CONTROL REGISTER 0 CONTROL REGISTER 1 DETECT REGISTER TONE CONTROL REGISTER CONTROL REGISTER 2 CONTROL REGISTER 3
CR0
MODULATION OPTION TRANSMIT PATTERN 1 DEVICE SIGNATURE 1 RXD/TXD CONTROL
0
MODULATION MODE ENABLE DETECT INTERRUPT RECEIVE DATA TRANSMIT ANSWER TONE
POWER ON
CHARACTER SIZE 1 (READ ONLY) CLK CONTROL
CHARACTER SIZE 0 (READ ONLY)
TRANSMIT ENABLE TEST MODE 1 CALL PROGRESS DETECT DTMF 1
ORIGINATE/ ANSWER TEST MODE 0 LONG LOOP DETECT DTMF 0 GUARD/ANS. TONE
CR1
001
1001
TRANSMIT PATTERN 0 DEVICE SIGNATURE 0 TRANSMIT GUARD TONE
BYPASS SCRAMBLER UNSCR. MARK DETECT TRANSMIT DTMF
RESET
DR
010
1010
CARRIER DETECT
ANSWER TONE DETECT DTMF 2
TONE
011
1011
DTMF 3
CR2
100
1100
RESERVED FOR FUTURE USE
CR3
101
1101
SPEAKER VOLUME 1
SPEAKER VOLUME 0
OFF-HOOK
X
X
X
X
X
SCRATCH REGISTER UART CONTROL REGISTER
SCR
110
1110
BIT 7
BIT 6
BIT 5 REQUEST TO SEND (RTS) (READ ONLY)
BIT 4 DATA TERM. READY (DTR) (READ ONLY)
BIT 3
BIT 2 DATA CARRIER DETECT (DCD)
BIT 1 DATA SET READY (DSR)
BIT 0 CLEAR TO SEND (CTS)
UCR
111
1111
TXCLK (READ ONLY)
X
RING INDICATOR (RI)
X = Undefined, mask in software 0 = Only write zero to this location
12
73K222AU Single-Chip Modem with UART
UART REGISTER BIT DESCRIPTIONS
RECEIVER BUFFER REGISTER (RBR) (READ ONLY) STNDLN: 0 1 ADDRESS: UA2 - UA0 = 000, DLAB = 0 UA3 - UA0 = 0000, DLAB = 0 This read only register contains the parallel received data with start, stop, and parity bits (if any) removed. The high order bits for less than 8 data bits/character will be set to 0. TRANSMIT HOLDING REGISTER (THR) (WRITE ONLY) STNDLN: 0 1 ADDRESS: UA2 - UA0 = 000, DLAB = 0 UA3 - UA0 = 0000, DLAB = 0 This write only register contains the parallel data to be transmitted. The data is sent LSB first with start, stop, and parity bits (if any) added to the serial bit stream as the data is transferred. INTERRUPT ENABLE REGISTER (IER) STNDLN: 0 ADDRESS: UA2 - UA0 = 001, DLAB = 0 1 UA3 - UA0 = 0001, DLAB = 0 UART SECTION
This 8-bit register enables the four types of interrupts of the UART to separately activate the chip Interrupt (INTRPT) output signal. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of the Interrupt Enable Register. Similarly, by setting the appropriate bits of this register to a logic 1, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and the active (high) INTRPT output from the chip. All other system functions operate in their normal manner, including the setting of the Line Status and Modem Status Registers. BIT NO. D0 D1 D2 D3 D4 NAME Received Data Transmitter Holding Register Empty Receiver Line Status Interrupt Modem Status 8250A/16450 CONDITION 1 1 1 1 1/0 DESCRIPTION This bit enables the Received Data Available Interrupt when set to logic 1. This bit enables the Transmitter Holding Register Empty Interrupt, when set to logic 1. This bit enables the Receiver Line Status Interrupt, when set to logic 1. This bit enables the Modem Status Register Interrupt when set to interrupt logic 1. Set for compatibility with 8250A/16C450 UARTS. Reset this bit to disable the gating of the INTRPT interrupt line with the DISTR signal which is needed for 8250B compatibility. These three bits are always logic 0.
D5 - D7
Not Used
0
13
73K222AU Single-Chip Modem with UART
INTERRUPT ID REGISTER (IIR) (READ ONLY) STNDLN: 0 1 ADDRESS: UA2 - UA0 = 010 UA3 - UA0 = 0010 UART SECTION
The IIR register gives prioritized information as to the status of interrupt conditions. When accessed, the IIR freezes the highest priority interrupt pending and no other interrupts are acknowledged until the particular interrupt is serviced by the CPU. BIT NO. D0 NAME Interrupt Pending CONDITION 0 DESCRIPTION This bit can be used in either a hardwired priortized or polled environment to indicate whether an interrupt is pending. When bit 0 is a logic 0, an interrupt is pending and the IIR contents may be used as a pointer to the appropriate interrupt service routine. When bit 0 is a logic 1, no interrupt is pending. These two bits of the IIR are used to identify the highest priority interrupt pending as indicated in the following table. These five bits of the IIR are always logic 0.
1 D1, D2 Interrupt ID bits 0, 1 Not Used Table below
D3 - D7
0
INTERRUPT PRIORITY TABLE D2 0 1 D1 0 1 D0 1 0 PRIORITY Highest None Receiver Line Status TYPE None Overrun Error, Parity Error, Framing Error or Break Interrupt Receive Data Available Transmit Holding Register Empty SOURCE RESET Reading the Line Status Register
1 0
0 1
0 0
Second Third
Receive Data Available Transmit Holding Register Empty
Reading the Rcvr. Buffer Register Reading IIR Register (if source of interrupt) or Writing to Transmit Holding Register Reading the Modem Status Register
0
0
0
Fourth
Modem Status
Clear to Send or Data Set Ready or Ring Indicator or Data Carrier Det.
14
73K222AU Single-Chip Modem with UART
LINE CONTROL REGISTER (LCR) STNDLN: 0 ADDRESS: UA2 - UA0 = 011 1 UA3 - UA0 = 0011 UART SECTION
The user specifies the format of the asynchronous data communications exchange via the Line Control Register. In addition to controlling the format, the user may retrieve the contents of the Line Control Register for inspection. This feature simplifies system programming and eliminates the need for separate storage in system memory of the line characteristics. BIT NO. D0 D1 NAME Word Length Select 0 Word Length Select 1 D1 0 0 1 1 D2 Number of Stop Bits 0 or 1 D0 0 1 0 1 CONDITION DESCRIPTION Bits D0 and D1 select the number of data bits per character as shown: Word Length 5 bits 6 bits 7 bits 8 bits This bit specifies the number of stop bits in each transmitted character. If bit 2 is a logic 0, one stop bit is generated in the transmitted data. If bit 2 is a logic 1 when a 5-bit word length is selected via bits 0 and 1, one-and-a-half stop bits are generated. If bit 2 is a logic 1 when either a 6, 7, or 8-bit word length is selected, two stop bits are generated. The receiver checks the first stop bit only, regardless of the number of stop bits selected. This bit is the Parity Enable bit. When bit 3 is a logic 1, a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and stop bit of the serial data. (The parity bit is used to produce an even or odd number of 1's when the data word bits and the parity bit are summed). This bit is the Even Parity Select bit. When bit 3 is a logic 1 and bit 4 is a logic 0, an odd number of logic 1's are transmitted or checked in the data word bits and parity bit. When bit 3 is a logic 1 and bit 4 is a logic 1, an even number of logic 1's are transmitted or checked.
D3
Parity Enable
1
D4
Even Parity Select
1 or 0
15
73K222AU Single-Chip Modem with UART
LINE CONTROL REGISTER (LCR) (continued) BIT NO. D5 NAME Stick Parity CONDITION 1 or 0 DESCRIPTION This bit is the Stick Parity bit. When bit 3 is a logic 1 and bit 5 is a logic 1, the parity bit is transmitted and checked by the receiver as a logic 0 if bit 4 is a logic 1 or as a logic 1 if bit 4 is a logic 0. D4 0 1 0 1 1 Parity ODD Parity EVEN Parity MARK Parity SPACE Parity Output of modem is set to a spacing state. When the modem is transmitting DPSK data if the Set Break bit is held for one full character (start, data, parity, stop) the break will be extended to 2 N + 3 space bits (where N = # data bits + parity bit + 1 start + 1 stop). Any data bits generated during this time will be ignored. See note below. This bit is the Divisor Latch Access Bit (DLAB). It must be set high (logic 1) to access the Divisor Latches of the baud generator during a Read or Write operation. It must be set low (logic 0) to access the Receiver Buffer, the Transmitter Holding Register, or the Interrupt Enable Register. UART SECTION
D5 0 0 1 1 D6 Set Break
D7
Divisor Latch Access Bit (DLAB)
1
NOTE: This feature enables the CPU to alert a terminal in a computer communications system. If the following sequence is followed, no erroneous or extraneous characters will be transmitted because of the break. 1. Load an all 0's pad character in response to THRE. 2. Set break in response to the next THRE. 3. Wait for the Transmitter to be idle. (TSRE = 1), and clear break when normal transmission has to be restored. During the break, the Transmitter can be used as a character timer to accurately establish the break duration.
16
73K222AU Single-Chip Modem with UART
MODEM CONTROL REGISTER (MCR) STNDLN: 0 ADDRESS: UA2 - UA0 = 100 1 UA3 - UA0 = 0100 UART SECTION
The MCR register controls the interface with the modem. Bits D1 and D0 are also available as read only bits in the UART Control Register in the Modem Registers. In single-port mode, bits D1 and D0 are available inverted at the RTS and DTR pins. BIT NO. D0 NAME DTR CONDITION 1 DESCRIPTION This bit controls the Data Terminal Ready (DTR) output. When bit 0 is set to a logic 1, the DTR output is forced to a logic 0. When bit 0 is reset to a logic 0, the DTR output is forced to a logic 1. This bit controls the Request to Send (RTS) output. When bit 1 is set to a logic 1, the RTS output is forced to a logic 0. When bit 1 is reset to a logic 0, the RTS output is forced to a logic 1. In single-port mode inactive unless loop = 1, then functions as below (D4). In dual-port mode the PRST pin is the logical OR of this bit and the RESET pin. Sets INTRPT pin to high impedance if STNDLN = 1. INTRPT output enabled. This bit provides a local loopback feature for diagnostic testing of the UART portion of the 73K222AU. When bit D4 is set to logic 1, the following occurs: 1. TXD is forced to mark, RXD is ignored. 2. The output of the Transmitter is looped to the Receiver. 3. The four modem control inputs to the UART (CTS, DSR, DCD, and RI) are ignored and the UART signals RTS, DTR, Enable Interrupt, and PRST are forced inactive. 4. The UART signals RTS, DTR, Enable Interrupt, and PRST are internally connected to the four control signals CTS, DSR, DCD and RI respectively. Note that the Modem Status Register Interrupts are now controlled by the lower four bits of the Modem Control Register. The interrupts are still controlled by the Interrupt Enable Register. D5 - D7 0 These bits are permanently set to logic 0.
* Note: The PRST bit has an upgraded function which was not included in the initial definition of the 73K222AU.
D1
RTS
1
D2
PRST* (OUT1 in 16C450) Enable Interrupt (OUT2 in 16C450) LOOP
1
D3 D4
0 1 1
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73K222AU Single-Chip Modem with UART
LINE STATUS REGISTER (LSR) STNDLN: 0 ADDRESS: UA2 - UA0 = 101 UART SECTION 1 UA3 - UA0 = 0101
This register provides status information to the CPU concerning the data transfer. BIT NO. D0 NAME DR CONDITION 1 DESCRIPTION The Data Ready (DR) bit is set to a 1 whenever a complete incoming character has been received and transferred into the Receiver Buffer Register. Data Ready is reset to 0 by reading the data in the Receiver Buffer Register or by writing a 0 into it from the processor. The Overrun Error (OE) bit indicates that the data in the Receiver Buffer Register was not read by the CPU before the next character was transferred into the Receiver Buffer Register, thereby destroying the previous character. The OE indicator is reset whenever the CPU reads the contents of the Line Status Register. The Parity Error (PE) bit indicates that the received character did not have the correct parity. The bit is reset to 0 whenever the CPU reads the Line Status Register. The Framing Error (FE) bit indicates that the received character did not have a valid stop bit. The FE indicator is reset whenever the CPU reads the contents of the Line Status Register. A framing error will not occur in DPSK receive from the modem due to the fact that missing stop bits are reinserted. The Break Interrupt (BI) bit indicates that a break has been received. A break occurs whenever the received data is held to 0 for a full data word (start + data + stop) or for two full data words when receiving in DPSK mode from the modem. The BI bit is reset to 0 whenever the CPU reads the Line Status Register. The Transmit Holding Register Empty (THRE) indicates that the Transmitter is ready to accept a new character for transmission. The THRE bit is reset when the CPU loads a character into the Transmit Holding Register. The Transmit Shift Empty (TSRE) indicates that both the Transmit Holding Register and the Transmit Shift Registers are empty. Always zero.
D1
OE
1
D2
PE
1
D3
FE
1
D4
BI
1
D5
THRE
1
D6
TSRE
1
D7
-
0
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73K222AU Single-Chip Modem with UART
MODEM STATUS REGISTER (MSR) (READ ONLY) STNDLN: 0 1 ADDRESS: UA2 - UA0 = 110 UA3 - UA0 = 0110 UART SECTION
This register provides the current state of the control signals from the modem. In addition, four bits provide change information. The CTS, DSR, DCD, and RI signals come from the UART Control Register if STNDLN = 0 and from the CTS, DSR, DCD and RI pins (inverted) if STNDLN = 1. This register is READ ONLY. The delta bits indicate whether the inputs have changed since the last time the Modem Status Register has been read. In Loop Mode CTS, DSR, RI and DCD are taken from RTS, DTR, PRST, and Enable Interrupt in the Modem Control Register respectively. BIT NO. D0 NAME DCTS CONDITION 1 DESCRIPTION This bit is the Delta Clear to Send (DCTS) indicator. Bit 0 indicates that the CTS input to the chip has changed state since the last time it was read by the CPU. This bit is the Delta Data Set Ready (DDSR) indicator. Bit 1 indicates that the DSR input to the chip has changed state since the last time it was read by the CPU. This bit is the Trailing Edge of the Ring Indicator (TERI) detector. Bit 2 indicates that the RI input to the chip has changed state. This bit is the Delta Data Carrier Detect (DDCD) indicator. Bit 3 indicates that the DCD input to the chip has changed state. This bit is the complement of the Clear To Send (CTS) input. If STNDLN = 0, this reflects the status of the UART Control Register bit. If bit 4 (loop) of the MCR is set to a 1, this bit is equivalent to RTS in the MCR. This bit is the complement of the Data Set Ready (DSR) input. If STNDLN = 0, this reflects the status of the UART Control Register bit. If bit 4 of the MCR is set to a 1, this bit is the equivalent of DTR in the MCR. This bit is the complement of the Ring Indicator (RI) input. If STNDLN = 0, this reflects the status of the UART Control Register bit. If bit 4 of the MCR is set to a 1, this bit is equivalent to PRST in the MCR. This bit is the complement of the Data Carrier Detect (DCD) If STNDLN = 0, this reflects the status of the UART Control Register bit. If bit 4 of the MCR is set to a 1, this bit is equivalent to Enable Interrupt in the MCR.
D1
DDSR
1
D2
TERI
1
D3
DDCD
1
D4
CTS
1
D5
DSR
1
D6
RI
1
D7
DCD
1
19
73K222AU Single-Chip Modem with UART
SCRATCH REGISTER (SCR) STNDLN: 0 ADDRESS: UA2 - UA0 = 111 1 UA3 - UA0 = 0111 UART SECTION
The Scratch Register is a dual port register which can be simultaneously accessed through both the UART bus and the modem bus. This provides the possibility for the modem controller to communicate directly with the central CPU. Note that if both processors write the Scratch Register, the data stored will be from whichever processor last wrote the register. DIVISOR LATCH (Least significant byte) (DLL) STNDLN: 0 ADDRESS: UA2 - UA0 = 000, DLAB = 1 DIVISOR LATCH (Most significant byte) (DLM) STNDLN: 0 ADDRESS: UA2 - UA0 = 001, DLAB = 1 DIVISOR LATCH VALUE VS. DATA RATE The Divisor Latch is two 8-bit write only registers which control the rate of the programmable baud generator. The programmable baud generator generates an output clock by dividing an internal 1.8432 MHz clock by the value stored in the divisor latch. This output clock has a value of 16X the data rate at which the modem will operate. This output clock is available at pin 21 under the control of bit 3 (D3) of the Modem Control Register 1. Upon loading either of the Divisor Latches the 16-bit device counter is immediately loaded, preventing long counts on initial load. The following table shows divisor values for common data rates. DESIRED DATA RATE 50 1 75 1 110 1 134.5 159 300 600 1200
1 1 2 3 1
1 UA3 - UA0 = 0000, DLAB = 1 1 UA3 - UA0 = 0001, DLAB = 1
DIVISOR USED FOR 16 x DATA RATE CLOCK 2304 1536 1047 857 768 384 192 96 64 58 48 32
% ERROR GENERATED
DESIRED DATA RATE 4800 7200 9600
DIVISOR USED FOR 16 x DATA RATE CLOCK 24 16 12 6 3 2
% ERROR GENERATED
0.058
19200 38400 56000
2.86
1. Data Rate valid for FSK transmission. 2. Data Rate valid for halfspeed DPSK transmission. 0.69 3. Data Rate valid for normal 1200 bit/s DPSK transmission.
1800 2000 2400 3600
20
73K222AU Single-Chip Modem with UART
MODEM REGISTER BIT DESCRIPTIONS CONTROL REGISTER (CR0) STNDLN: 0 ADDRESS: MA2 - MA0 = 000 BIT NO. D0 NAME Answer/Originate 1 UA3 - UA0 = 1000 CONDITION 0 1 D1 Transmit Enable 0 1 DESCRIPTION Selects Answer Mode (transmit in high band, receive in low band). Selects Originate Mode (transmit in low band, receive in high band). Disables transmit output at TXA. Enables transmit output at TXA. NOTE: Answer tone and DTMF TX control require Transmit Enable. If Transmit Enable is on, call progress and answer tone detector interrupts are masked. D2, D3 Character Size 0, 1 These bits are read only. These bits represent the character size. The character size is determined by the UART Line Control Register and includes data, parity (if used), one start bit, and one stop bit. D3 0 0 1 1 D4 Power ON D2 0 1 0 1 Character length 8-bit character 9-bit character 10-bit character 11-bit character This bit controls the power down mode of the 73K222AU, the analog, and most digital portions of the chip. The digital interface is active during power down. 0 1 D5 D6 D7 Modulation Mode Reserved Modulation Option 0 1 0 0 1 0 1 FSK: Power down mode. Normal operation. DPSK FSK Must be written as zero. DPSK: 1200 bit/s 600 bit/s 103 mode V.21 mode MODEM SECTION
21
73K222AU Single-Chip Modem with UART
CONTROL REGISTER (CR1) STNDLN: 0 ADDRESS: MA2 - MA0 = 001 BIT NO. D0, D1 NAME Test Mode 1 UA3 - UA0 = 1001 CONDITION D1 0 0 D0 0 1 Selects normal operating mode. Analog Loopback Mode. Loops the transmitted analog signal back to the receiver, and causes the receiver to use the same center frequency as the Transmitter. To squelch the TXA pin, transmit enable bit must be forced low. Selects remote digital loopback. Received data is looped back to transmit data internally, and RXD is forced to a mark. Data in TXD is ignored. Selects half-duplex. Internally performs a logical AND of TXD and RXD to send to the UART receiver. Both transmit and receive characters will occur at the Receiver Buffer Register. Selects normal operation. Resets modem to power down state. All Control Register bits (CR0, CR1, TONE) are reset to zero. The output of the clock pin will be set to the crystal frequency. CLK pin output is selected to be an 11.0592 MHz crystal echo output. CLK pin output is selected to be 16 x the Data Rate set by the UART divisor latch. Selects normal operation. DPSK data is passed through scrambler. Selects Scrambler Bypass. DPSK data is routed around scrambler in the transmit path. DESCRIPTION MODEM SECTION
1
0
1
1
D2
Reset
0 1
D3
CLK Control (Clock Control)
0 1
D4
Bypass Scrambler
0 1
22
73K222AU Single-Chip Modem with UART
CONTROL REGISTER (CR1) (continued) BIT NO. D5 NAME Enable Detect Interrupt CONDITION 0 DESCRIPTION Disables interrupts generated by Detect Register bits D1 - D4 at INT pin in dual-port mode, or at INTRPT pin in single-port mode. All interrupts normally disabled in power down modes. Enables interrupts generated by Detect Register bits D1 - D4 at INT pin in dual-port mode, or at INTRPT pin in single-port mode. An interrupt will be generated with a change in status of DR bits D1 - D4. The answer tone and call progress detect interrupts are masked when the TX enable bit is set. Carrier detect is masked when TX DTMF is activated. All interrupts will be disabled if the device is in power down mode. The interrupt is reset when the DR register is read. D6 0 1 0 1 Selects normal data transmission as controlled by the state of the TXD pin. Selects an alternating mark/space transmit pattern for modem testing. Selects a constant mark transmit pattern. Selects a constant space transmit pattern. MODEM SECTION
1
D6, D7
Transmit Pattern
D7 0 0 1 1
23
73K222AU Single-Chip Modem with UART
DETECT REGISTER (DR) STNDLN: 0 ADDRESS: MA2 - MA0 = 010 BIT NO. D0 D1 NAME Long Loop Call Progress Detect 1 UA3 - UA0 = 1010 CONDITION 0 1 0 1 DESCRIPTION Indicates normal received signal. Indicates low received signal level (< -38 dBm). No call progress tone detected. Indicates presence of call progress tones. The call progress detection circuitry is activated by energy in the normal 350 to 620 Hz call progress bandwidth. No answer tone detected. Indicates detection of 2225 Hz answer tone in Bell mode or 2100 Hz in CCITT mode. The device must be in Originate Mode for detection of answer tone for normal operation. For CCITT answer tone detection, bit D0 of the Tone Register must be set. No carrier detected in the receive channel. Carrier has been detected in the receive channel. No unscrambled mark detected. Indicates detection of unscrambled marks in the received data. A valid indication requires that unscrambled marks be received for > 165.5 13.5 ms. Continuously outputs the received data stream. This data is the same as that output on the RXD pin, but it is not disabled when RXD is tri-stated. D7 Device Signature 0, 1 0 0 1 D6 0 1 0 Product Identified 73K212U (special order only) 73K221U (special order only) 73K222AU MODEM SECTION
D2
Answer Tone Received
0 1
D3 D4
Carrier Detect Unscrambled Marks
0 1 0 1
D5
Receive Data
D6, D7
24
73K222AU Single-Chip Modem with UART
TONE CONTROL REGISTER (TONE) STNDLN: 0 ADDRESS: MA2 - MA0 = 011 1 UA3 - UA0 = 1011 MODEM SECTION
The Tone Control Register contains information on the tones that are transmitted. Tones are transmitted only if the Transmit Enable bit is set. The priority of the transmit tones are: 1) DTMF, 2) Answer, 3) FSK, 4) Guard. BIT NO. D0 NAME DTMF 0 / Answer/ Guard Tone D6 X X X 1 1 D0, D1, D2, D3 DTMF CONDITION D5 X 1 1 0 0 D4 1 0 0 0 0 D0 X 0 1 0 1 DESCRIPTION D0 interacts with bits D6, D5, and D4 as shown: Transmit DTMF tones. Select 2225 Hz answer tone (Bell). Select 2100 Hz answer tone (CCITT). Select 1800 Hz guard tone. Select 550 Hz guard tone.
Table below: Programs 1 of 16 DTMF tone pairs that will be transmitted when TX DTMF and TX enable bit (CR0, bit D1) is set. Tone encoding is shown below. KEYBOARD EQUIVALENT 1 2 3 4 5 6 7 8 9 0 * # A B C D DTMF CODE D3 D2 D1 D0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 TONES LOW HIGH 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633
25
73K222AU Single-Chip Modem with UART
TONE CONTROL REGISTER (TONE) (continued) BIT NO. D4 NAME TX DTMF (Transmit DTMF) CONDITION 0 1 DESCRIPTION Disable DTMF. Activates DTMF. The selected DTMF tones are transmitted continuously when this bit is high. TX DTMF overrides all other transmit functions. D0 X 0 D5 interacts with bit D0 as shown. Disables answer tone generator. Enables answer tone generator. A 2225 Hz answer tone will be transmitted continuously when the transmit enable bit is set. The device must be in answer mode. Enables a 2100Hz answer operation same as above. Disables guard tone generator. Enables guard tone generator. (See D0 for selection of guard tones). D7 0 0 1 Function is dependant on status of STNDLN pin. RXD is output data received by modem, TXD is serial output of UART. For monitoring only. RXD is electrically an input, but the signal is ignored, TXD is forced to a mark. RXD is serial input to UART, TXD is serial output of UART. tone generator, with MODEM SECTION
D5
TX ANS (Transmit Answer Tone)
D5 0 1
1 D6 TX Guard (Transmit Guard Tone) RXD/TXD Control
STNDLN
1 0 1
D7
0 1 1
CONTROL REGISTER (CR3) STNDLN: 0 ADDRESS: MA2 - MA0 = 101 D0 - D4 D5 D6, D7 Not Used Off Hook Speaker Volume 0, 1
1 UA3 - UA0 = 1101 Not presently used. 0 1 D7 0 0 1 1 D6 0 1 0 1 Relay driver open. Open drain driver pulling low. Speaker volume control status. Speaker off -24 dB -12 dB 0 dB
26
73K222AU Single-Chip Modem with UART
SCRATCH REGISTER (SCR) STNDLN: 0 ADDRESS: MA2 - MA0 = 110 1 UA3 - UA0 = 1110 MODEM SECTION
The Scratch Register is a dual-port register which can be accessed either through the UART bus or the modem bus. It can be used for a communication path outside the data stream. UART CONTROL REGISTER (UCR) STNDLN: 0 ADDRESS: MA2 - MA0 = 111 1 UA3 - UA0 = 1111
The UART Control Register contains the handshaking signals necessary for the microprocessor to communicate with the central CPU through the UART. BIT NO. D0 NAME CTS CONDITION 1 DESCRIPTION In dual-port mode, CTS, DSR, DCD and RI are writeable locations which can be read through the 16C450 port in the Modem Status Register. In the single-port mode, D0 - D3 are ignored and the information for the Modem Status Register comes directly from the external pins.
D1 D2
DSR DCD
1 1
D3 D4 D5 D6 D7
RI DTR RTS Not Used TXCLK
1 1 1 DTR and RTS are read only versions of the same register bits in the Modem Control Register. TXCLK is the clock that the UART puts out with TXD. The falling edge of TXCLK is coincident with the transitions of data on TXD. TXCLK can also be used for the microprocessor to send synchronous data independent of the UART by forcing data patterns using CR1 bits 6 and 7 before the rising edge of TXCLK.
Clock
NOTE: Control Register 2 (CR2) is reserved for future products and is disabled.
27
73K222AU Single-Chip Modem with UART
ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS TA = -40C to 85C, VDD = 5V 10%, unless otherwise noted. PARAMETER VDD Supply Voltage Storage Temperature Soldering Temperature (10 sec.) Applied Voltage RATING 7 -65 to 150 260 -0.3 to VDD +0.3 UNIT V C C V
NOTE: All inputs and outputs are protected from static charge using built-in, industry standard protection devices and all outputs are short-circuit protected. RECOMMENDED OPERATING CONDITIONS PARAMETER VDD, Supply Voltage TA, Operating Free-Air Temperature External Component (Refer to application drawing for placement.) VREF Bypass Capacitor 2 Bias Setting Resistor 1 ISET Bypass Capacitor 2 VDD Bypass Capacitor XTL1 Load Capacitor XTL2 Load Capacitor Input Clock Variation Hybrid Loading R1 R2 C TXA Hybrid Loading 1. Optional for minimum worst case current consumption. 2. Minimum for optimized system layout; may require higher values for noisy environments. See Figure 3 600 600 0.033 F
2
CONDITION
MIN 4.5 -40
NOM 5
MAX 5.5 85
UNIT V C
(VREF to GND) (Placed between VDD and ISET pins) ISET pin to GND (VDD to GND) From pin to GND From pin to GND (11.0592 MHz)
0.1 1.8 0.1 0.1 40 20 -0.01 +0.01 2 2.2
F M F F pF pF %
28
73K222AU Single-Chip Modem with UART
DC ELECTRICAL CHARACTERISTICS TA = -40C to +85 C, VDD = 5V 10%, unless otherwise noted. PARAMETER IDD, Supply Current IDDA, Active IDDA, Active IDD1, Power-Down IDD2, Power-Down Digital Inputs Input High Current Input Low Current Input Low Voltage Input High Voltage Input High Voltage Pull Down Current Input Capacitance Digital Outputs Output High Voltage VOL other outputs CLK Output OH Output OH Output Capacitance Inputs CLK Analog Pins RXA Input Resistance RXA Input Capacitance 200 25 k pF Input Capacitance
Maximum capacitive load to pin
CONDITION ISET Resistor = 2 M ISET = GND CLK = 11.0592 MHz CLK = 19.200 kHz IIH IIL VIL VIH VIH
RESET PIN
MIN
NOM 8 8 3 2
MAX 12 15 4 3 100
UNIT mA mA mA mA A A V V V
VI = VDD VI = 0 Except RESET & XTL1 RESET & XTL1 -200
0.8 2.0 3.0 5 30 10
A pF V V V V V V A pF pF
VOH
IOUT = - 1 mA IOUT = 3.2 mA IOUT = 1.6 mA IOUT = 3.2 mA IOUT = 20 mA IOUT = 10 mA VO = 0V
2.4
VDD 0.4 0.4 0.6 1.0 0.5
VOL UD0-UD7 and INTRPT VOL VOL VOL
Offstate Current INTRPT pin
-20
20 10 15
29
73K222AU Single-Chip Modem with UART
ELECTRICAL SPECIFICATIONS (continued) DYNAMIC CHARACTERISTICS AND TIMING TA = -40C to +85C, VDD = 5V 10%, unless otherwise noted. PARAMETER DPSK Modulator Carrier Suppression Output Amplitude Measured at TXA ANS TONE 2225 or 2100 Hz DPSK TX Scrambled Marks FSK Dotting Pattern FSK Tone Error DTMF Generator Freq. Accuracy Output Amplitude Output Amplitude Long Loop Detect Demodulator Dynamic Range Call Progress Detector Detect Level Reject Level Delay Time Hold Time Hysteresis Carrier Detect Threshold Delay Time Hysteresis Hold Time Answer Tone Detector Detect Level Threshold Delay Time Hold Time Detect Frequency Range In FSK mode -70 dBm0 to -30 dBm0 Step -30 dBm0 to -70 dBm0 Step -49.5 20 10 -2.5 -42 45 30 +2.5 dBm0 ms ms % -30 dBm0 to -70 dBm0 Step DPSK or FSK Receive Data -70 dBm0 to -30 dBm0 Step -49 15 2 10 3.0 24 -42 45 dBm0 ms dB ms 2-Tones in 350-600 Hz Band 2-Tones in 350-600 Hz Band -70 dBm0 to -30 dBm0 Step -30 dBm0 to -70 dBm0 Step 27 27 2 -39 0 -46 80 80 dBm0 dBm0 ms ms dB Low Band, not in V.21 mode High Band, not in V.21 mode DPSK or FSK DPSK or FSK -.25 -10 -8 -40 45 -9 -7 .25 -8 -6 -32 % dBm0 dBm0 dBm0 dB Bell 103 or V.21 55 -11 -11 -11 -10.0 -10.0 -10.0 -9 -9 -9 5 dB dBm0 dBm0 dBm0 Hz CONDITION MIN NOM MAX UNIT
1. All units in dBm0 are measured at the line input to the transformer. The interface circuit inserts an 8 dB loss in the transmit path (TXA1 - TXA2 to line), and a 3 dB loss in the receive path (line to RXA).
30
73K222AU Single-Chip Modem with UART
DYNAMIC CHARACTERISTICS AND TIMING (continued) PARAMETER Speaker Output Gain Error Output Swing SPKR Carrier VCO Capture Range Capture Time Recovered Clock Capture Range Data Delay Time Guard Tone Generator Tone Accuracy Tone Level (Below DPSK Output) Harmonic Distortion 550 or 1800 Hz 550 Hz 1800 Hz 700 to 2900 Hz -20 -4.0 -7.0 -3.0 -6.0 +20 -2.0 -5.0 -60 Hz dB dB dB % of Center Frequency Analog data in at RXA pin to receive data valid at RXD pin. -625 30 +625 50 ppm ms Originate or Answer -10 Hz to +10 Hz Carrier Frequency change assumed -10 40 10 100 Hz ms 10K||50 pF LOAD 5% THD -1 2.75 +1 dB VP CONDITION MIN NOM MAX UNIT
SERIAL BUS INTERFACE (See Figure 4) The following times are for CL = 100 pF. PARAMETER Data out from Read Data out after Clock Data Float after Read Clock High after Read Write Width Data Setup Before Clock Data Hold after Clock Write after Clock Address setup before Control Address Hold after Control
1 1
MIN
NOM
MAX 70 110 40
UNIT ns ns ns ns ns ns ns ns ns ns ns ns
0 65 0 55 60 0 100 0 0 10000
Address setup before Write LOW Address Hold after Write HIGH 1. Control is later of falling edge of RD or DCLK.
31
73K222AU Single-Chip Modem with UART
ELECTRICAL SPECIFICATIONS (continued) PARALLEL BUS INTERFACE (See Figure 5) The following times are for CI = 100 pF. PARAMETER RC TDIW TDDD THZ** TRA TRCS TAR* TCSR WC TDOW TDS TDH** TWA TWCS TAW* TADS TAS TAH TCS TCH TRC TWC TAD * ** Read Cycle = TAD + TRC DISTR Width Delay DISTR to Data (read time) DISTR to Floating Data Delay Address Hold after DISTR Chip select hold after DISTR DISTR Delay after Address DISTR Delay after Chip Select Write Cycle = TAW + TDOW + TWC DOSTR Width Data Setup Data Hold Address Hold after DOSTR Chip select hold after DOSTR DOSTR delay after Address Address Strobe Width Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Read Cycle Delay Write Cycle Delay Address to Read Data 40 40 110 20 20 22 20 140 40 15 5 20 20 0 20 MIN 240 30 45 50 5 20 15 20 140 40 25 5 5 20 15 20 15 10 0 10 0 40 40 110 MAX MIN 340 30 45 40 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Dual-Port Mode
Single-Port Mode
DOSTR delay after Chip Select
TAR and TAW are referenced from the falling edge of either CS@ or DISTR or DOSTR, whichever is later. THZ and TDH are referenced from the rising edge of CS@ or DISTR or DOSTR, whichever is earlier.
32
73K222AU Single-Chip Modem with UART
TXA1
R1 RXA
C TXA2
600 R2 1:1
(Nominal Telephone Line Impedance)
TA Hybrid Loading Analog Interface Hybrid Loading
FIGURE 3: TXA Hybrid Loading Analog Interface Hybrid Loading
READ MODE
DCLK
TRCK 1 TACR ADDRESS 1 TCAR ADDR 1 TCAR 1 TACR DATA TRD D0 D1 D6 D7 TCKD TRDF
WRITE MODE DCLK TWW TCKW TACW ADDRESS ADDR TCAW
TDCK
TCKH
DATA
D0
D1
D2
D6
D7
FIGURE 4: Modem Serial Bus Timing
33
73K222AU Single-Chip Modem with UART
TADS TRC TAW TWC
(STNDLN = 1) TAH TAS ADDRESS UA2 (UA3)-UA0 VALID VALID FOR NO TCS TCH LOW FOR NO TAR TAR TDIW TAW WC TRA TAS VALID TCS TCH LOW FOR NO VALID FOR NO TWA TAH
TCSW TAW TDOW OR
RC TDDD TAD DATA UD7-UD0 READ DATA WRITE DATA THZ TDS TDH
FIGURE 5: UART Bus Timing
34
73K222AU Single-Chip Modem with UART
TYPICAL PERFORMANCE CHARACTERISTICS The 73K222AU was designed using an integrated analog/digital architecture that offers optimum performance over a wide range of line conditions. The 73K222AU utilizes the circuit design proven in TDK Semiconductor's 73K222L one-chip modem, with added enhancements which extend low signal level performance and increase immunity to spurious noise typically encountered in integral bus applications. The 73K222AU provides excellent immunity to the types of disturbances present with usage of the dial-up telephone network. The following curves show representative Bit Error Rate performance under various line conditions. BER vs. S/N This test measures the ability of the modem to function with minimum errors when operating over noisy lines. Since some noise is generated by even the best dial-up lines, the modem must operate with as low a S/N ratio as possible. Optimum performance is shown by curves that are closest to the zero axis. A narrow spread between curves for the four line conditions indicates minimal variation in performance when operating over a range of line qualities and is typical of high performance adaptive equalization receivers. High band receive data is typically better than low band due to the inherent design of PSK modems.
73K222AU BER vs S/N
10-2 HIGH BAND RECEIVE -30 dBm DPSK OPERATION 10-2
73K222AU BER vs RECEIVE LEVEL
HIGH BAND RECEIVE DPSK OPERATION C2 LINE
10-3 600 BPS
1200 BPS 10-3
C2 C1 OR 3002
BIT ERROR RATE
C2 10-4 C1 OR 3002 FLAT
FLAT
BIT ERROR RATE
10-4
S/N = 10.8 dB 10-5 10-5
S/N = 15 dB 10-6 2 4 6 8 10 12 14 10-6 10 0 -10 -20 -30 -40 -50 SIGNAL TO NOISE (dB) RECEIVE LEVEL (dBm)
35
73K222AU Single-Chip Modem with UART
BER vs. Receive Level This measures the dynamic range of the modem. As signal levels vary widely over dial-up lines, the widest dynamic range possible is desirable. The minimum Bell specification calls for 36 dB of dynamic range. S/N ratios were held constant at the indicated values while receive level was lowered from very high to very low signal levels. The "width of the bowl" of these curves taken at the 10-4 BER point is a measure of the dynamic range. BER vs. Carrier Offset This parameter indicates how the modem performance is impacted by frequency shifts encountered in normal PSTN operation. Flat curves show no performance degradation from frequency offsets. The K-Series devices use a 2nd order carrier tracking phase-locked-loop, which is insensitive to carrier offsets in excess of 10 Hz. The Bell network specifications allow as much as 7 Hz offset, and the CCITT specifications require modems to operate with 7 Hz of offset.
10-2
73K222AU BER vs CARRIER OFFSET
HIGH BAND RECEIVE DPSK OPERATION
10-3
BIT ERROR RATE
10-4
3002 11.5 dB S/N
10-5
C2 10.8 dB S/N
10-6 12 8 4 0 -4 -8 -12
SIGNAL TO NOISE (dB)
APPLICATION
The 73K222AU includes additional circuitry to greatly simplify integral modem designs in either of two different configurations. The single-port mode represents the most efficient implementation for an integral modem. Figure 9 shows a typical schematic using this mode. In this configuration, the 73K222AU transfers data and commands through the single parallel port. All modem control is provided by the main CPU, eliminating the need for an external microcontroller and supporting components. The 73K222AU is unique in that access to both the UART and modem sections is possible through the UART port. Also shown is a separate serial port, which can be used independent of the modem function when the modem section is inactive. Figure 10 shows a more conventional integral modem design, in which a local microprocessor handles modem supervision, allowing the modem function to be transparent to the main processor. Inclusion of the hybrid drivers, audio volume control, and off hook relay driver reduces component count for a highly efficient design. In either mode of operation, the 73K222AU's ability to operate from a single +5 volt power supply eliminates the need for additional supply voltages and keeps power usage to a minimum. (See Figure 9 & 10: Typical Integral Applications Single and Dual-Port Modes.)
36
U2 R8 3 VDD 40 C4 0.1 F +5 IRQ 5 INTRPT GND C1 39 pF C2 18 pF A0 A31 39 UA0 38 UA1 RXD 22 13 14 2 11 6 A4 A27 5 8 7 14 +1 F C13 73K222AU 1 4 3 2 A5 A26 A6 A25 A7 A24 A8 A23 A9 A22 J4 COM1 U4 LS04 a +5V 14 +5 IN4708 B13 B14 18 D8 A9 27 UD0 28 UD1 RXA TXA1 3.9V 3 R1 600 C11 0.022 F TXA2 4 3.9V R6 1 Fuseable T1 K1 NO MOV1 V250LA20A 29 UD2 30 UD3 31 UD4 32 UD5 33 UD6 16 D1 A8 D2 A7 D3 A6 D4 A5 D5 A4 D6 A3 D7 A2 +5 35 D5 IN4004 36 C11 D2 0.22 F 250 VDC A T R LINE R5 1 Fuseable R7 22 K 7 R2 22 K 8 U8 4N35 COM2 D1 IN4004 12 11 +5 1 OPTIONAL DIGITAL SERIAL PORT 37 UA2 12 UA3 23 +5 TXD 7 6 A1 A30 A2 A29 A3 A28 24 STNDALN 15 XTL2 25 X1 XTL1 11.0592 MHz ISET 9 20
+5
PC BUS
37
b 34 UD7 C9 0.1 F R3 5.1K 19 VREF 17 SPKR 0.1 F C6 RST 0.001 C12 35 RESET MIDCOM +5 U5 671-8005 LM386 220 F 3 6 C14 R9 5 + SPKR 0.047 2 7 8 4 0.1 F R4 10 C10
AEN A11
A1 A T R A1 PHONE
73K222AU Single-Chip Modem with UART
FIGURE 9: 73K222AU Typical Integral Application Single-Port Mode
U2 +5 R7 3 J3 5 INTRPT GND C1 39 pF C2 18 pF 31 +5 N/C 10 RXD 30 ALE TXD 14 15 16 S1-3 S1-4 17 S1-2 S1-1 11 A0 A31 39 UA0 38 UA1 37 UA2 23 DATA P3.5 P3.6 P3.7 DCLK 23 4 P1.3 P1.4 P0 P1.7 P2 13 R2 +5 9 0.22 F 250 VDC IN4708 D2 C11 R7 22 K 22 K IN4004 D1 P1.6 P1.5 X1 X2 RST 5 26 8 7 MA2 MA1 MA0 C13 21 19 N/C 18 12 14 6 13 7 14 +1 F 1 12 8 8 LINES UNUSED 8 LINES PORTS U8 4N35 A3 A28 6 5 4 3 2 A4 A27 A5 A26 A6 A25 A7 A24 A8 A23 A9 A22 J4 12 11 +5 1 U3 LS30 11 P1.1 2 22 P1.0 1 P3.4 TXD 7 6 RXD A1 A30 A2 A29 24 STNDALN 15 XTL2 29 N/C 25 X1 XTL1 11.0592 MHz ISET 9 VSS 20 1F 20 VDD C8 0.1 F 40 + C4 COM 2 INT COM 1 INT VDD 40 U1
+5
PC BUS B25 IRQ3 IRQ4 B3 C3 B1 +5V 10 F B24
73K222AU Single-Chip Modem with UART
8053
73K222AU
INT 2
COM1 U4 LS04 a +5V 14 7 B13 B14 18 D8 A9 27 UD0 28 UD1 RXA TXA1 3 R1 600 3.9V C11 0.022 F TXA2 4 3.9V +5 3 R9 2 T1 K1 NO 29 UD2 30 UD3 31 UD4 32 UD5 33 UD6 34 UD7 16 D1 A8 D2 A7 D3 A6 D4 A5 D5 A4 D6 A3 D7 A2 +5 35 D5 IN4004 36 PRST 8
COM2
38
AEN A11 b U4 LS04 RESET B2 c U4 LS04 d C9 0.1 F R3 5.1K 19 VREF 17 SPKR 0.1 F C6 RST 0.001 C12 10 MIDCOM U5 671-8005 LM386 220 F 6 C14 5 + SPKR 0.047 7 8 4 0.1 F R4 10 C10
J1 A T FUSE F1 R LINE
A1 MOV1 V250LA20A A T R A1 PHONE
FIGURE 10: 73K222AU Typical Integral Application Dual-Port Mode
73K222AU Single-Chip Modem with UART
MECHANICAL SPECIFICATIONS
40-Pin DIP
44-Pin PLCC
0.695 (17.655) 0.685 (17.399)
0.075 (1.905) 0.065 (1.651) 0.165 (4.191) 0.200 (5.080)
PIN NO. 1 IDENT.
0.050 (1.270) 0.016 (0.406) 0.020 (0.508) 0.590 (14.986) 0.630 (16.002)
0.045 (1.140) 0.020 (0.508)
0.695 (17.655) 0.685 (17.399)
0.656 (16.662) 0.650 (16.510)
0.656 (16.662) 0.650 (16.510)
39
73K222AU Single-Chip Modem with UART
PACKAGE PIN DESIGNATIONS
(Top View)
CAUTION: Use handling procedures necessary for a static sensitive component.
1 ( )/ TXA1 TXA2 INTRPT RXD TXD ( ) PRST ISET RESET ( ) / DCLK (UA3) / MA2 ( ( ) / MA1 ) / MA0 STNDLN RXA SPKR 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VREF GND 19 20
40 39 38 37 36 35
VDD UA0 UA1
Parentheses indicate single-port mode.
) TXA2 TXA1 /(
VDD
UA2
UA0
UA1
UA2
N/C
N/C
6 INTRPT 7 8 9 10 11 12 13 14 15 16 UD7 RXD UD6 UD5 UD4 UD3 UD2 UD1 UD0 / (N/C) STNDLN XTL1 XTL2 /( DATA / ( CLK ) ) ( ( ( ( TXD ) / PRST ISET RESET ) / DCLK ) / MA2 ) / MA1
5
4
3
2
1
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 UD7 UD6 UD5 UD4 UD3 UD2 UD1 UD0 N/C
34 33 32 31 30 29 28 27 26 25 24 23 22 21
(CTS) / MA0
17 29 18 19 20 21 22 23 24 25 26 27 28
(DTR) / DATA
SPKR
XTL2
600-Mil 40-Pin DIP 73K222AU-IP
44-Pin PLCC 73K222AU-IH
ORDERING INFORMATION
PART DESCRIPTION 73K222AU 40-Pin Plastic Dual In-Line 44-Pin Plastic Leaded Chip Carrier 73K222AU-IP 73K222AU-IH 73K222AU-IP 73K222AU-IH ORDER NUMBER PACKAGING MARK
No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK Semiconductor Corporation, and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders. TDK Semiconductor Corporation, 2642 Michelle Drive, Tustin, CA 92780-7019, (714) 508-8800, FAX: (714) 508-8877 TDK Semiconductor Corporation 04/24/00- rev.D
40
(
)/
XTL1
GND
RXA
CLK
N/C

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